1. Field of the Invention
The present disclosure relates to an image sensor, and more particularly, to an image sensor in which one or more reference pixel rows are shared to eliminate row noises from different image pixel rows and to reduce reference pixel area, thereby preventing from the drop of frame rate when eliminating the row noises by a digital approach or avoiding extra noises and reducing circuit area when eliminating the row noises by an analog approach.
2. Description of the Prior Art
In general, in an image sensor, a pixel readout circuit such as a correlation double sampling (CDS) is utilized to read image pixel rows row by row so as to generate reset values and sampling values. Consequently, when different image pixel rows are read, even though the patterns of the different image pixel rows are actually identical, pixel readout circuit may still read different reset values and sampling values owing to random noises, more specifically, because external electrical potential like system voltages, grounded electrical potential and bias reference voltages are disturbed by the random noises. In this case, the conventional image sensor is usually equipped with a reference pixel array in order to eliminate the row noises caused by the random noises.
Please refer to FIG. 1, which is a schematic diagram illustrating a conventional image sensor 10. As shown in FIG. 1, the image sensor 10 comprises a pixel unit 100, a pixel readout circuit 102, a control circuit 104, a row control circuit 106, a column decoder 108, a differential amplifier 110, an analog-to-digital converter 112 (ADC) and an image signal processor 114. The pixel unit 100 further comprises an image pixel array 116 and an optical-black-area pixel array 118 and optionally comprises a reference pixel array 120. The reference pixel array 120 is disposed after the last pixel (or before the first pixel) of each row of the image pixel array 116.
In short, after photodiodes of each of the pixels in the image pixel array 116 are exposed to light during an image sensing process, charges are induced by the photodiodes and stored in the corresponding sensing capacitors. Subsequently, the control circuit 104 controls the row control circuit 106, the column decoder 108 and the pixel readout circuit 102, such that the pixel readout circuit 102 samples the image pixel array 116 row by row and generates the reset values and the sampling values of each pixel. Then, the difference between the reset values and the sampling values is amplified, converted from analog to digital form and processed by the differential amplifier 110, the analog-to-digital converter 112 and the image signal processor 114. During the image sensing process, the optical-black-area pixel array 118 and the reference pixel array 120 are shielded against light in order to respectively provide dark current and the information of random noises when the pixel readout circuit 102 performs sampling; therefore, the pixel readout circuit 102 or the image signal processor 114 can respectively suppress dark current and random noises by analog or digital approaches.
To be more specific, please refer to FIGS. 2A to 2C. FIG. 2A is a schematic diagram illustrating an image sensor 20 which embodies the image sensor 10 shown in FIG. 1 in the prior art. FIG. 2B is a schematic diagram illustrating a pixel 202 shown in FIG. 2A. FIG. 2C is a timing schematic diagram illustrating the signals shown in FIGS. 2A and 2B. In short, as shown in FIGS. 2A to 2C, the image pixel array 116 comprises the image pixel rows R1-Rn and the image pixel columns C1-Cm. The pixel 202 may be any pixel in the image pixel array 116. For example, the pixel 202 can be located at a point of any intersection of the image pixel rows R1-Rn and the image pixel columns C1-Cm. The pixel readout circuit 200 comprises the sample-and-hold circuits SHC1-SHCm, which respectively correspond to the image pixel columns C1-Cm.
In this structure, during the image sensing process, a photodiode 204 exposed to light generates charges and the charges are stored in a sensing capacitor 206 to serve as a sensing signal. When a bias reference voltage BIAS is high and after a row selecting signal chooses the image pixel row with the pixel 202 and hence a row switch RS is switched on, a pixel reset switch RST and a reset switch SHR are turned on in sequence. Subsequently, according to a system voltage VDD, which is not the sensing signal stored by the sensing capacitor 206, a transistor 208 is conducted so that charges are stored in a reset capacitor CR to serve as a reset value. Then, a pixel transmission switch TX and a sampling switch SHS are turned on in sequence, such that the transistor 208 is conducted according to the sensing signal and the charges are stored in a sampling capacitor CS to serve as a sampling value. When the reset values and the sampling values are read, an average reference voltage signal switch set ARVS may respectively control a terminal of the reset capacitor CR and the sampling capacitor CS to respectively connect a reference voltage VREF with the switches SW2 and SW1, thereby eliminating non-ideal factors such as dark current. Finally, a switch CB is conducted and a column selection circuit CSC controls a switch in the corresponding column to be turned on, such that the difference between the reset values and the sampling values stored in the corresponding reset capacitor CR and the corresponding sampling capacitor CS are transmitted to the differential amplifier 110 for the following processes.
However, because the image sensor 20 does not comprise the reference pixel array 120 for the pixel readout circuit 200 or the image signal processor 114 to compensate for random noises, and because merely a capacitor CB is added at an input terminal of the bias reference voltage BIAS within a bias circuit 210 of the pixel readout circuit 200 to prevent the random noises of the bias circuit 210 from entering the pixel readout circuit 200, row noises may still remain if any other external electrical potential brings random noises into the image.
Besides, please refer to FIG. 3, which is a schematic diagram illustrating an image sensor 30 which embodies the image sensor 10 in the prior art. Since the image sensor 30 is partially similar to the aforementioned image sensor 20, the same numerals and symbols denote components and signals of similar functions in FIG. 3 and the following description. The main difference between the image sensor 30 and the image sensor 20 is that the image sensor 30 further comprises the reference pixel array 120, which comprises the reference pixel rows RR1-RRn and the reference pixel columns Cm+1-Cm+k. A pixel readout circuit 300 further comprises the sample-and-hold circuits SHCm+1-SHCm+k respectively corresponding to the reference pixel columns Cm+1-Cm+k in the reference pixel array 120. The reference pixel columns Cm+1-Cm+k are disposed after the last pixels of the image pixel columns C1-Cm—namely, the reference pixel rows RR1-RRn are disposed after the image pixel rows R1-Rn. The pixel 202 may also be any reference pixel of the reference pixel array 120, only that the reference pixel is shielded against light and does not sense light during the image sensing process. The sample-and-hold circuits SHCm+1-SHCm+k and the sample-and-hold circuits SHC1-SHCm have identical structure.
In this structure, during the image sensing process, the image pixel array 116 is exposed to light and the optical-black-area pixel array 118 and the reference pixel array 120 are shielded against light or set as the non-light-sensing pixel. The pixel readout circuit 300 then utilizes the sample-and-hold circuits SHC1-SHCm and SHCm+1-SHCm+k to respectively read the image pixel rows R1-Rn and the reference pixel rows RR1-RRn row by row, such that the corresponding reset values, the corresponding sampling values, the corresponding reference reset values and the corresponding reference sampling values are obtained by means of the method similar to that of the pixel readout circuit 200 mentioned above. Then, the differences between the reset values and the sampling values and the differences between the reference reset values and the reference sampling values are amplified, converted from analog to digital form and processed by the differential amplifier 110, the analog-to-digital converter 112 and the image signal processor 114. In this case, when the image signal processor 114 performs image signal process, the average of the differences of the reference reset values and the reference sampling values of the pixels corresponding to the specific reference pixel row in the corresponding reference pixel rows RR1-RRn is subtracted from the differences of the reset values and the sampling values of the pixels of the corresponding specific image pixel row in the image pixel rows R1-Rn by the digital approach so as to eliminate the disturbance of external electrical potential owing to random noises.
Moreover, in the U.S. Pat. No. 8,310,569, each of the sample-and-hold circuits further comprises an amplifier, and the corresponding average capacitor replaces the corresponding sample-and-hold circuit of the reference pixel column. The average capacitors may store charges by means of the method similar to that of reading the reset values and the sampling values illustrated above and generate an average reference voltage by averaging the charges to each amplifier so as to directly provide the average reference voltage to another terminal of the reset capacitor and the sampling capacitor by the analog approach, thereby eliminating the disturbance of external electrical potential owing to random noises.
In addition, in the U.S. Pat. No. 8,310,569, the reference pixel array merely further comprises reference pixels, and each of the reference pixels respectively corresponds to one of the image pixel columns. Subsequently, the pixel readout circuit may directly generate each of the corresponding reference voltages by means of the method similar to that of reading the reset values and the sampling values illustrated above so as to directly provide the reference voltages respectively to another terminal of the reset capacitor and the sampling capacitor by the analog approach, thereby eliminating the disturbance of external electrical potential owing to random noises.